1. Field of the Invention
The present invention relates to a CDMA (Code Division Multiple Access) communication system and in particular, to a multistage interference canceller which extracts a signal component for each user by eliminating signal components for other users from a received signal containing spread modulated signals for a plurality of users.
2. Description of the Prior Art
In recent years, a CDMA communication system has been attracted attentions among communication systems which are used for mobile communication systems. In the CDMA communication system, a transmission side transmits a spectrum spread signal which is obtained by spectrum-spreading a user signal with a spread code whose chip rate is tens to hundreds times as fast as the bit rate of the user signal, and a reception side obtains the original user signal by spectrum-despreading the spectrum spread signal with the same spread code as the transmission side. Here, a user signal to be transmitted as information is referred to as a symbol, and a unit constituting a spread code is referred to as a chip.
Although a single user receiver which demodulates a signal for a single user is generally used as a receiver in a reception side, a multiple user receiver which simultaneously demodulates signals for a plurality of users is also used as a receiver in a reception side. For the purpose of improving a communication quality when simultaneously demodulating signals for a plurality of users in a multiple user receiver, a multistage interference canceller is proposed.
A multistage interference canceller is such an apparatus that decreases interference from the signals of the other users by performing plural times such an operation in which symbol replica signals which are the same as the signal components of the other users are generated, and the symbol replica signals are subtracted from a received signal to be demodulated before demodulating the received signal containing signals for a plurality of users with a spread signal for a specified user. There are two types of multistage interference canceller, i.e., a serial type and a parallel type.
Next, the structure of a conventional parallel type multistage interference canceller will be explained with reference to FIG. 4.
This conventional parallel type multistage interference canceller has a structure of M stages by N users. As shown in FIG. 4, this conventional parallel type interference canceller comprises IEUs (Interference Estimation Units) 11 . . . 1N as many as Mxc3x97N (M stagesxc3x97N users), delay circuits (D) 21 . . . 2Mxe2x88x921 as many as Mxe2x88x921, subtractors 31 . . . 3Mxe2x88x921 as many as Mxe2x88x921, and path search units 241 . . . 24N as many as N.
Each of delay circuits (D) 21 . . . 2Mxe2x88x921 inputs received signal rin or residual signal 7 to delay it by a prescribed period. The period by which each of delay circuits (D) 21 . . . 2Mxe2x88x921 delays received signal rin or residual signal 7 is the same as the period required to generate symbol replica signals 51 . . . 5Mxe2x88x921 and chip replica signals 6 in IEU 11 . . . IEU 1N.
Each of subtractors 31 . . . 3Mxe2x88x921 subtracts a sum of chip replicas 6 in each stage from received signal rin or residual signal 7 which is outputted from each of delay circuits 21 . . . 2Mxe2x88x921 in order to output residual signal 7 thus subtracted to the next stage.
FIG. 5 shows the structure of IEU 11 in the first stage and input signals thereto, and FIG. 6 shows the structure of IEU 11 in the second stage and input signals thereto. IEU 11 . . . IEU 1N are different from one another only in that spread codes which are set to them are correspondent to respective users among the first to the N-th users, and their operations are the same. Therefore, the explanation of the structure and operation of IEU 11 will be made below.
IEU 11 comprises despreader/transmission line estimator 101 . . . 108, rake/diversity synthesizer 11, symbol replica generator 12, and chip replica generator 13. Here, the explanation will be made assuming that IEU 11 . . . IEU 1N are of 2-branchxc3x974-path structure.
IEU 11 in the first stage and IEU 11 in the second stage are different from each other in that signals inputted thereto are different from each other, and their structures are the same. IEU 11 in the M-th stage is the same as IEUs 11 in the other stages in structure except that chip replica generator 13 is deleted from IEU 11 in the M-th stage.
Each of despreader/transmission line estimator 101 . . . 108 performs despreading, adds a symbol replica signal 51, and estimates a transmission line every path and every branch on the basis of a path timing indicated by path timing signal 28.
IEU 11 to IEU 1N are correspondent to the signals of the first to the N-th users, respectively. Despreaders/transmission line estimators 101 . . . 108 perform despreading with spread codes of respective users.
Rake/diversity synthesizer 11 performs rake synthesis and diversity synthesis on signals from despread/transmission line estimator 101 . . . 108 to output synthesized signal as one signal.
Symbol replica generator 12 generates symbol replica signal 51 or 52 on the basis of a signal from rake/diversity synthesizer 11 to output symbol replica signal 51 or 52 to IEU 11 in the next stage.
Chip replica generator 13 generates chip replica signal 6 by re-spreading symbol replica 51 generated in symbol replica generator 12.
In accordance with the structure explained above, IEU 11 in the first stage generates symbol replica signal 51 to be outputted to the second stage and chip replica signal 6 to be outputted to the second stage from received signal rin on the basis of path timing signal 28. IEU 11 in the second stage generates symbol replica signal 52 to be outputted to the third stage and chip replica signal 6 to be outputted to the third stage from residual signal 7 and symbol replica signal 51 from the first stage on the basis of path timing signal 28.
Path search units 241 . . . 24N are different from one another only in that spread codes which are set thereto are correspondent to respective users among the first to the N-th users, and their operations are the same. Therefore, path search unit 241 will be explained.
Path search unit 241 comprises path timing detector 14 as shown in FIG. 7. Path timing detector 14 inputs received signal rin, performs path searching by using a spread code corresponding to the first user, and outputs the searched path timing as path timing signal 28.
Next, the operation of the conventional multistage interference canceller as shown in FIG. 4 will be explained.
Upon inputting received signal rin, path timing detector 14 in path search unit 241 performs path searching by using the spread code corresponding to the first user and outputs the obtained path timing as path timing signal 28. IEU 11 in the first stage despreads received signal rin every path and every branch on the basis of the path timing indicated by path timing signal 28, and also performs transmission line estimation, rake synthesis, and diversity synthesis to generate symbol replica 51, and chip replica 6.
Subtractor 31 subtracts the sum of chip replicas outputted from IEUs 11 . . . 1N from received signal rin from delay circuit 21 to output residual signal 7 to the second stage.
IEU 11 in the second stage despreads residual signal 7 every path and every branch on the basis of the path timing indicated by path timing signal 28, adds symbol replica signal 51 to residual signal 7 which has been despread, and performs transmission line estimation, rake synthesis, and diversity synthesis to generate symbol replica 52, and chip replica 6.
Further, in the third and the following stages, the same operation as the second stage is performed. The M-th stage which is the final stage outputs the first to the N-th user signals from IEUs 11 . . . 1N, respectively.
In the conventional multistage interference canceller as explained above, path search units 241 . . . 24N are provided only in the first stage. IEUs 11 . . . 1N perform processes up to the final stage using path timing signal 28 generated by a single path search in path search units 241 . . . 24N. However, if a reception power of a certain user signal is weak, the user signal is subject to interferences from the other user signals. Because path search units 241 . . . 24N perform path searching using received signal rin from which interferences from the other user signals are not get rid of, when detecting a path timing of a user signal whose reception power is weak, there is generated such a case that an accurate path timing is not detected and an miss-detection takes place. As a result, the reception performance of the CDMA reception apparatus deteriorates due to the miss-detection of the path timings.
The conventional multistage interference canceller explained above has a disadvantage that it""s reception performance deteriorates due to miss-detection of path timings when a reception power of a certain user signal is weak.
In order to overcome the aforementioned disadvantages, the present invention has been made and accordingly, has an object to provide a multistage interference canceller which is improved in reception performance by detecting accurate path timings even for user signals whose reception powers are weak.
According to a first aspect of the present invention, there is provided a multistage interference canceller for extracting each user signal from a received signal containing spectrum spread signals of a plurality of users by removing signal components of the users other than each user, said canceller comprising: a first stage comprising: a plurality of first interference estimation units provided for respective users, each of said first interference estimation units generating a first symbol replica signal and a first chip replica signal from said received signal on the basis of primary path timings, said first symbol replica signal being the same as a signal component of each user, and said first chip replica signal being a respread signal from said first symbol replica signal; a first delay circuit for outputting said received signal after delaying said received signal by a first prescribed period; and a first subtractor for subtracting a sum of a plurality of said first chip replica signals which are outputted from a plurality of said first interference estimation units from said received signal which is outputted from said first delay circuit to output the residual as a first residual signal; a plurality of path search units provided for respective users, each of said path search units comprising: means for setting path timings which are obtained by performing path search on said received signal using a spread signal as said primary path timings; means for setting path timings which are obtained by performing path search on said first residual signal supplied from said first stage as temporal secondary path timings of paths having said primary path timings; and means for setting said temporal secondary path timing as a secondary path timing for each path of which signal-to-interference ratio measured is lower than a first prescribed threshold and of which a time difference between said primary path timing thereof and said temporal secondary path timing thereof is shorter than a second prescribed threshold, and for setting said first path timing as a secondary path timing for each path of which signal-to-interference ratio measured is not lower than said first prescribed threshold or of which a time difference between said primary path timing thereof and said temporal secondary path timing thereof is not shorter than said second prescribed threshold; a second stage comprising: a plurality of second interference estimation units provided for respective users, each of said second interference estimation units generating a second symbol replica signal and a second chip replica signal from said first residual signal supplied from said first stage and said first symbol replica signal on the basis of secondary path timings, said second symbol replica signal being the same as a signal component of each user, and said second chip replica signal being a respread signal from said second symbol replica signal; a second delay circuit for outputting said first residual signal after delaying said first residual signal by a second prescribed period; and a second subtractor for subtracting a sum of a plurality of said second chip replica signals which are outputted from a plurality of second interference estimation units from said first residual signal which is outputted from said second delay circuit to output the residual as a second residual signal to be supplied to a third stage; and a third stage comprising: a plurality of third interference estimation units provided for respective users, each of said third interference estimation unit generating said user signal from said second residual signal supplied from said second stage and said second symbol replica signal supplied from said second stage.
According to a second aspect of the present invention, there is provided a multistage interference canceller for extracting each user signal from a received signal containing spectrum spread signals of a plurality of users by removing signal components of the users other than each user, said canceller comprising: a first stage comprising: a plurality of first interference estimation units provided for respective users, each of said first interference estimation units generating a first symbol replica signal and a first chip replica signal from said received signal or a first subtracted signal on the basis of primary path timings, said first symbol replica signal being the same as a signal component of each user, and said first chip replica signal being a respread signal from said first symbol replica signal; a plurality of first delay circuits connected one another in series, each of said first delay circuit outputting said received signal or a signal inputted thereto after delaying said received signal or the signal inputted thereto by a first prescribed period; and a plurality of first subtractors, each of said first subtractors being provided after each of said first delay curcuits and subtracting said first chip replica signal which is outputted from each of said first interference estimation units from a signal outputted from a preceding first delay circuit to output the residual as said first subtracted signal to a succeeding first delay circuit and a corresponding first interference estimation unit; a plurality of path search units provided for respective users, each of said path search units comprising: means for setting path timings which are obtained by performing path search on said received signal using a spread signal or said first subtracted signal as said primary path timings; means for setting path timings which are obtained by performing path search on a residual signal which is an output from the last of said first subtractors or a second subtracted signal as temporal secondary path timings of paths having said primary path timings; and means for setting said temporal secondary path timing as a secondary path timing for each path of which signal-to-interference ratio measured is lower than a first prescribed threshold and of which a time difference between said primary path timing thereof and said temporal secondary path timing thereof is shorter than a second prescribed threshold, and for setting said first path timing as a secondary path timing for each path of which signal-to-interference ratio measured is not lower than said first prescribed threshold or of which a time difference between said primary path timing thereof and said temporal secondary path timing thereof is not shorter than said second prescribed threshold; a second stage comprising: a plurality of second interference estimation units provided for respective users, each of said second interference estimation units generating a second symbol replica signal and a second chip replica signal from said first residual signal or said second subtracted signal and said first symbol replica signal on the basis of secondary path timings, said second symbol replica signal being the same as a signal component of each user, and said second chip replica signal being a respread signal from said second symbol replica signal; a plurality of second delay circuits connected one another in series, each of said second delay circuits outputting said first residual signal or a signal inputted thereto after delaying said first residual signal or the signal inputted thereto by a second prescribed period; and a plurality of second subtractors, each of said second subtractors being provided after each of said second delay circuits and subtracting said second chip replica signal which is outputted from each of said second estimation units from a signal outputted from a preceding second delay circuit to output the residual as said second subtracted signal to a succeeding second delay circuit, a corresponding second interference estimation unit, and a corresponding means for setting path timings; and a third stage comprising: a plurality of third interference estimation units provided for respective users, each of said third interference estimation units generating said user signal and a third chip replica signal from a second residual signal which is an output from the last of said second subtractors or a third subtracted signal and said second symbol replica signal on the basis of secondary path timings, and said third chip replica signal being a respread signal from said user signal; a plurality of third delay circuits connected one another in series, each of said third delay circuits outputting said second residual signal or a signal inputted thereto after delaying said second residual signal or the signal inputted thereto by a third prescribed period; and a plurality of third subtractors, each of said third subtractors being provided after each of said third delay circuits and subtracting said third chip replica signal which is outputted from each of said third estimation units from a signal outputted from a preceding third delay circuit to output the residual as said third subtracted signal to a succeeding third delay circuit and a corresponding third interference estimation unit.
These and other objects, features and advantages of the present invention will become more apparent in the light of the following detailed description of the best mode embodiments thereof, as illustrated in the accompanying drawings.